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is61wv20488all is61/64wv20488bll copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. b 08/04/2010 2m x 8 high-speed cmos static ram august 2010 features ? high-speed access times: 8, 10, 20 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe op- tions ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single power supply C v d d 1.65v to 2.2v (is61wv20488all) speed = 20ns for vcc = 1.65v to 2.2v C v d d 2.4v to 3.6v (is61/64wv20488bll) speed = 10ns for vcc = 2.4v to 3.6v speed = 8ns for vcc = 3.3v + 5% ? packages available: C 48-ball minibga (9mm x 11mm) C 44-pin tsop (type ii) ? industrial and automotive temperature support ? lead-free available description the issi is61wv20488all/bll and is64wv20488bll are very high-speed, low power, 2m-word by 8-bit cmos static ram. the is61wv20488all/bll and is64wv20488bll are fab- ricated using issi 's high-performance cmos technol- ogy. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. the is61wv20488all/bll and is64wv20488bll operate from a single power supply and all inputs are ttl-compatible. the is61wv20488all/bll and is64wv20488bll are available in 48 ball mini bga and 44-pin tsop (type ii) packages. functional block diagram a0-a20 ce oe we 2m x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll pin descriptions a0-a20 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 data input / output v d d power gnd ground nc no connection 48-pin mini bga (m ) (9mm x 11mm) 44-pin tsop (type ii ) 1 2 3 4 5 6 a b c d e f g h nc nc nc gnd v dd nc nc a18 oe nc nc nc nc nc a19 a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 ce i/o1 i/o3 i/o4 i/o5 we a11 nc i/o0 i/o2 v dd gnd i/o6 i/o7 a20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc a20 a18 a17 a16 a15 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a14 a13 a12 a11 a10 a19 nc nc 44 43 42 41 pin configuration
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.5 to v d d + 0.5 v v d d v d d relates to gnd C0.3 to 4.0 v t s t g storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we ce oe i/o operation v d d current not selected x h x high-z i s b 1 , i s b 2 (power-down) output disabled h l h high-z i c c read h l l d o u t i c c write l l x d i n i c c capacitance (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c i/o input/output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v d d = 3.3v.
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll operating range ( v d d ) (is61wv20488bll) (1) range ambient temperature v d d (8 n s ) v d d (10 n s ) commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial C40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range ( v d d ) (is64wv20488bll) range ambient temperature v d d (10 n s ) automotive C40c to +125c 2.4v-3.6v operating range ( v d d ) (is61wv20488all) ran ge ambient temperature v d d (20 n s ) commercial 0c to +70c 1.65v-2.2v industrial C40c to +85c 1.65v-2.2v automotive C40c to +125c 1.65v-2.2v
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll dc electrical characteristics (over operating range) v d d = 2.4v-3.6v symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1.0 ma 1.8 v v o l output low voltage v d d = min., i o l = 1.0 ma 0.4 v v i h input high voltage 2.0 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width 2.0 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 3.3v + 5% symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C4.0 ma 2.4 v v o l output low voltage v d d = min., i o l = 8.0 ma 0.4 v v i h input high voltage 2 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width 2.0 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 1.65v-2.2v symbol parameter test conditions v d d min. max. unit v o h output high voltage i o h = -0.1 ma 1.65-2.2v 1.4 v v o l output low voltage i o l = 0.1 ma 1.65-2.2v 0.2 v v i h input high voltage 1.65-2.2v 1.4 v d d + 0.2 v v i l (1) input low voltage 1.65-2.2v C0.2 0.4 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width 2.0 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width 2.0 ns). not 100% tested.
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll ac test loads figure 1. 319 ? 5 pf including jig and scope 353 ? output 3.3v figure 2. : / = 50? 1.5v 50? including jig and scope ac test conditions (high speed) p arameter unit unit unit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) )nput0ulse ,evel 6to 6 d d -0.3v 0.4v to v d d -0.3v 0.4v to v d d -0.2v )p 2isad a 4is s s s )p ad/p 4iig 6 d d /2 v d d /2 + 0.05 v d d /2 ad 2c ,v6 2 ) /p ,ad 3igsad 3igsad 3igsad
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 120 95 90 ma supply current i o u t = 0 ma, f = f m a x ind. 125 100 100 auto. 140 140 typ. (2) 60 i c c 1 operating v d d = max., com. 35 30 30 ma supply current i o u t = 0 ma, f = 0 ind. 35 40 40 auto. 60 70 i s b 1 ttl standby current v d d = max., com. 30 30 30 ma (ttl inputs) v i n = v i h or v i l ind. 35 35 35 ce v i h , f = 0 auto. 70 70 i s b 2 cmos standby v d d = max., com. 20 20 15 ma current (cmos inputs) ce v d d C 0.2v, ind. 25 25 20 v i n v d d C 0.2v, or auto. 70 70 v i n 0.2v , f = 0 typ. (2) 4 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll read cycle switching characteristics (1) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t r c read cycle time 8 10 ns t a a address access time 8 10 ns t o h a output hold time 2 2 ns t a c e ce access time 8 10 ns t d o e oe access time 5.5 6.5 ns t h z o e (2) oe to high-z output 3 4 ns t l z o e (2) oe to low-z output 0 0 ns t h z c e (2 ce to high-z output 0 3 0 4 ns t l z c e (2) ce to low-z output 3 3 ns t p u power up time 0 0 ns t p d power down time 8 10 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll read cycle switching characteristics (1) (over operating range) -20 ns symbol parameter min. max. unit t r c read cycle time 20 ns t a a address access time 20 ns t o h a output hold time 2.5 ns t a c e ce access time 20 ns t d o e oe access time 8 ns t h z o e (2) oe to high-z output 0 8 ns t l z o e (2) oe to low-z output 0 ns t h z c e (2 ce to high-z output 0 8 ns t l z c e (2) ce to low-z output 3 ns t p u power up time 0 ns t p d power down time 20 ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) (ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce = v i l . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) (ce = oe = v i l ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll write cycle switching characteristics (1,3) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t w c write cycle time 8 10 ns t s c e ce to write end 6.5 8 ns t a w address setup time 6.5 8 ns to write end t h a address hold from write end 0 0 ns t s a address setup time 0 0 ns t p w e 1 we pulse width (oe = high) 6.5 8 ns t p w e 2 we pulse width (oe = low) 8.0 10 ns t s d data setup to write end 5 6 ns t h d data hold from write end 0 0 ns t h z w e (2) we low to high-z output 3.5 5 ns t l z w e (2) we high to low-z output 2 2 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. shaded area product in development
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll write cycle switching characteristics (1,2) (over operating range) -20 ns symbol parameter min. max. unit t w c write cycle time 20 ns t s c e ce to write end 12 ns t a w address setup time 12 ns to write end t h a address hold from write end 0 ns t s a address setup time 0 ns t p w e 1 we pulse width (oe = high) 12 ns t p w e 2 we pulse width (oe = low) 17 ns t s d data setup to write end 9 ns t h d data hold from write end 0 ns t h z w e (3) we low to high-z output 9 ns t l z w e (3) we high to low-z output 3 ns notes: 1. tes t conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll ac waveforms write cycle no. 1 (1,2) (ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v i h . ac waveforms write cycle no. 2 (1,2) (we controlled: oe is high during write cycle)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll ac waveforms write cycle no. 3 (we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
16 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll data retention waveform (ce controlled) v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd 1.65v 1.4v data retention mode data retention switching characteristics symbol parameter test condition min. max. unit v d r v d d orata 2etention 3eeata2etention 7aveorm 6 i d r ata 2etention urrent 6 d d = 1.2v, ce v d d C 0.2v ind. 25 ma auto. 60 typ. (1) 3 t s d r ata2etention3etup ime 3ee ata2etention 7aveorm ns t r d r 2ecover ime 3eeata2etention 7aveorm t r c ns note: 4ypical valuesaremeasuredat 6 d d 6 a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 17 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll ordering information industrial range: -40c to +85c voltage range: 2.4v to 3.6v s peed (ns) order part no. package 10 (8 1 ) is61wv20488bll-10mi 48 mini bga (9mm x 11mm) is61wv20488bll-10mli 48 mini bga (9mm x 11mm), lead-free is61wv20488bll-10ti tsop (type ii) is61wv20488bll-10tli tsop (type ii), lead-free note: 1. speed = 8ns for v d d = 3.3v + 5%. speed = 10ns for v d d = 2.4v to 3.3v. industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 20 IS61WV20488ALL-20MI 48 mini bga (9mm x 11mm) is61wv20488all-20ti tsop (type ii) automotive range: -40c to +125c voltage range: 2.4v to 3.6v speed (ns) order part no. p ackage 10 is64wv20488bll-10ma3 48 mini bga (9mm x 11mm) is64wv20488bll-10mla3 48 mini bga (9mm x 11mm), lead-free is64wv20488bll-10ta3 tsop (type ii)
18 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/2 1 /2008
integrated silicon solution, inc. www.issi.com 1-800-379-4774 19 rev. b 08/04/2010 is61wv20488all, is61/64wv20488bll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outlin e

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